Show understanding of Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) processors
Understand differences between RISC and CISC processors
Understand interrupt handling on CISC and RISC processors
Show understanding of the importance and use of pipelining and registers in RISC processors
Show understanding of the four basic computer architectures: SISD, SIMD, MISD, MIMD
Show understanding of the characteristics of massively parallel computers
Show understanding of concept of a virtual machine
Give examples of role of virtual machines and understand benefits and limitations
📖 Prior Knowledge Required
Understanding of CPU components and the Fetch-Decode-Execute cycle
Knowledge of registers and their functions
Basic understanding of machine code and assembly language
Understanding of computer memory hierarchy
Knowledge of operating system basics
🌟 Did You Know?
A microprocessor, also known as the Central Processing Unit (CPU), is the brain of the computer. It reads instructions from memory that tell the computer what to do. The Instruction Set Architecture (ISA) is the set of basic instructions that a processor understands, consisting of Opcode (operational code) and Operand.
1. Complex Instruction Set Computer (CISC)
CISC stands for Complex Instruction Set Computer. CISC processors have a larger set of instructions with many addressing modes. These processors are designed with a full set of instructions to provide functions in the most efficient way.
📖 Key Characteristics of CISC
Capacity to perform multi-step operations or addressing modes within one instruction set
CPU design where one instruction works several low-level acts
Can include floating-point mathematical calculations and graphics-handling instructions
Instructions can perform complex tasks that take more than one cycle to execute
Efficient in terms of number of instructions per program
Lower demand for code storage and RAM compared to RISC
Requires more transistors to handle instruction complexity
1.1 CISC Architecture Philosophy
CISC architecture is based on single complex instructions which need to be converted by the processor into a number of sub-instructions to carry out the required operation.
📝 CISC Example: Adding Two Numbers
Suppose we wish to add two numbers A and B together:
ADD A, B
This is a single instruction that requires several sub-instructions (multi-cycle) to carry out the addition operation. The result: x := x + y is stored back in the first operand.
💡 Exam Tip
CISC methodology leads to shorter coding (than RISC) but may lead to more work being carried out by the processor. The design philosophy is to carry out a given task with as few lines of assembly code as possible!
2. Reduced Instruction Set Computer (RISC)
RISC stands for Reduced Instruction Set Computer. RISC processors have a reduced or smaller number of computer instructions than CISC, allowing them to operate at a higher speed, performing more millions of instructions per second (MIPS).
📖 Key Characteristics of RISC
Smaller instruction set with more simple instructions
Each instruction takes one clock cycle to execute
More suitable for pipelining
By removing unnecessary instructions and optimising pathways, provides outstanding performance
Requires a fraction of the power demand of CISC devices
Used in portable devices due to power efficiency (e.g., smartphones, tablets, Apple iPod)
2.1 RISC Design Philosophy
The primary goal of RISC processors is to make hardware simpler. The design philosophy is built on the use of less complex instructions, which is done by breaking up assembly code instructions into a number of simpler single-cycle instructions.
📝 RISC Example: Adding Two Numbers
To carry out addition of two numbers A and B:
LOAD X, A ← loads value of A into register X
LOAD Y, B ← loads value of B into register Y
ADD A, B ← takes values from X and Y and adds them
STORE Z ← result stored in register Z
Each instruction requires one clock cycle. Separating commands such as LOAD and STORE reduces the amount of work done by the processor, leading to faster processor performance.
💡 Exam Tip
RISC approach: Increases number of instructions per program but decreases number of cycles per instruction. Optimisation is done through the use of pipelining!
3. Differences Between CISC and RISC Processors
Feature
CISC
RISC
Instruction set size
Large
Small
Instruction complexity
Complex
Simple
Clock cycles per instruction
Multiple (multi-cycle)
One (single-cycle)
Instruction length
Variable-length
Fixed-length
Instruction formats
Many formats
Small number of formats
Addressing modes
More addressing modes
Fewer addressing modes
Memory addressing
Many types of instructions address memory
Only LOAD and STORE address memory
General-purpose registers
Fewer
More (multiple register sets)
Control unit
Microprogrammed
Hard-wired
Pipelining
More difficult
Easier
Compiler complexity
Less complex
More complex
Power usage
Higher
Lower
Cost
Higher
Lower
Memory use
Less (fewer instructions)
More (more instructions)
Design emphasis
Hardware
Software
Cache arrangement
Unified cache
Split cache (data and instructions)
Typical devices
Laptops, desktops
Smartphones, tablets
🧠 Memory Trick: CISC vs RISC
CISC = Complex → More instructions, multi-cycle, variable length
Think: RISC is like a sports car (fast, efficient, simple) while CISC is like a luxury car (feature-rich but complex)
4. Interrupt Handling on RISC and CISC
An interrupt is a signal emitted by a device attached to a computer or from a program within the computer. It requires the operating system to stop and figure out what to do next. An interrupt temporarily stops or terminates a service or a current process.
4.1 Interrupt Handling Without Pipelining
📝 Sequential Processing Interrupt Handling
Each instruction is handled sequentially before the next one can start
Once processor detects an interrupt (at end of fetch-execute cycle), current program is temporarily stopped
Status of each register is stored
Processor can be restored to original status after interrupt is serviced
4.2 Interrupt Handling With Pipelining
⚠️ Important: Pipeline Complexity
With pipelining, there is added complexity: as the interrupt is received, there could be a number of instructions still in the pipeline.
📝 Two Approaches to Handle Interrupts in Pipelining
Approach 1: Discard Pipeline Contents
Discard all instructions in the pipeline except the last instruction in write-back (WB) stage
Apply interrupt handler routine to remaining instruction
Once serviced, processor restarts with next instruction in sequence
Approach 2: Store Pipeline Contents (Alternative)
Contents of five stages can be stored in registers
All current data stored, allowing processor to be restored to previous status
Processor resumes exactly where it left off after interrupt serviced
4.3 RISC vs CISC Interrupt Handling
Feature
CISC
RISC
Instruction complexity
Complex instructions with built-in interrupt support
Pipelining is one of the less complex ways of improving computer performance. It allows several instructions to be processed simultaneously without having to wait for previous instructions to be completed.
📖 What is Pipelining?
Process of carrying out multiple instructions concurrently
Each instruction is at a different stage of the fetch-decode-execute cycle
One instruction can be fetched while previous one is being decoded and the one before is being executed
In the case of a branch, the pipeline is flushed
Like a modern assembly line in a car factory - each stage performs a specific task
5.1 The Five Stages of Pipelining
📝 Five Pipeline Stages
IF (Instruction Fetch): Fetch the instruction from memory
ID (Instruction Decode): Decode the instruction to be executed
OF (Operand Fetch): Fetch operands from registers
IE (Instruction Execute): Execute the instructions
WB (Write Back): Write the result to register or memory
🌟 Pipelining Efficiency Example
Consider a program with six instructions (A, B, C, D, E, F):
Without pipelining: 30 clock cycles (6 × 5 stages)
With pipelining: Only 10 clock cycles needed!
By the time instruction 'A' has completed, instruction 'F' is at first stage
6. Pipelining in RISC Processors
RISC (Reduced Instruction Set Computer) processors are designed for pipelining efficiency. Their architecture provides several key features that support effective pipelining.
📖 Key Features Supporting Pipelining in RISC
Each instruction takes one clock cycle (or close to it)
Fixed-length instructions make decoding easier
Limited instruction set reduces complexity and stage duration
Large number of general-purpose registers reduces memory access
Hard-wired control unit allows faster instruction execution
6.1 Role of Registers in RISC Pipelining
Registers are fast, temporary storage inside the CPU. RISC processors rely heavily on registers for operand storage rather than accessing RAM.
📝 How Registers Support Pipelining
Intermediate values are stored in registers between stages
Register usage reduces memory bottlenecks, allowing pipelining to run smoothly
All operations can be done efficiently within the CPU using registers
Example:
Instruction A loads value into Register R1
Instruction B adds R1 + R2 and stores result in R3
All of these can be done efficiently within the CPU using registers - no need to access slower RAM!
6.2 Benefits of Pipelining
Advantage
Explanation
Increased throughput
Multiple instructions handled at once
Better use of CPU components
Fetch, decode, and execute units are all in use simultaneously
Reduced idle time
No waiting between stages
Faster execution
Even if individual instructions don't run faster
❌ Common Mistake
Don't confuse pipelining with making each instruction faster - pipelining doesn't make individual instructions execute quicker! Instead, it increases the overall throughput by processing multiple instructions simultaneously at different stages.
7. Computer Architectures
A computer architecture is the design and structure of a computer system. It describes how it fetches, processes, and stores data and instructions. Each architecture is categorised as Single or Multiple Instruction stream, and Single or Multiple Data stream.
7.1 SISD - Single Instruction, Single Data
📖 SISD Architecture
One processor executes one instruction on one data stream at a time
Traditional serial (non-parallel) architecture
Each task is processed in sequential order
Since there is a single processor, this architecture does not allow for parallel processing
Used in basic, single-core processors and older generation computers
SISD Advantages
SISD Disadvantages
Requires less power
Speed limited like single-core processors
No complex communication protocol between cores
Not suitable for larger applications
7.2 SIMD - Single Instruction, Multiple Data
📖 SIMD Architecture
One instruction is applied to multiple pieces of data at once
Uses many processors - each executes the same instruction but with different data inputs
All processing units perform the same operation in parallel
Often referred to as array processors
Ideal for graphics and scientific computation
Used in modern GPUs (Graphics Processing Units)
Example: Image Brightness Adjustment
Suppose the brightness of an image made up of 4000 pixels needs to be increased. With SIMD, 4000 small processors (one per pixel) can each alter the brightness of each pixel by the same amount at the same time!
8. MISD and MIMD Architectures
8.1 MISD - Multiple Instruction, Single Data
📖 MISD Architecture
Multiple processors execute different instructions on the same data stream
An uncommon architecture rarely used in practice
Primarily used for fault tolerance in safety-critical systems
Different systems perform operations on the data and all results must agree
Used in flight control systems where fault detection is critical
Example: American Space Shuttle flight control system
⚠️ Important: MISD Usage
MISD is not used commercially for general computing. Its primary application is in specialised systems where fault tolerance is critical - if one processor fails, others can take over or detect errors.
8.2 MIMD - Multiple Instruction, Multiple Data
📖 MIMD Architecture
Multiple autonomous processors execute different instructions on different data
Most modern multi-core processors use this model
Allows full concurrent processing of independent tasks
Processors can work independently or as part of shared memory space
Flexible and scalable for parallel programs
Used in multi-core CPUs, distributed systems, and cloud computing
Architecture
Instruction Stream
Data Stream
Used In
SISD
Single
Single
Standard sequential processors
SIMD
Single
Multiple
Vector processing, GPUs
MISD
Multiple
Single
Specialised fault-tolerant systems
MIMD
Multiple
Multiple
Multi-core processors, parallel systems
9. Massively Parallel Computers
Massively parallel computers are systems made up of thousands of processors working simultaneously to solve a single large problem. Each processor executes part of a program, and results are combined to produce the final output.
📖 Key Characteristics
Thousands of processors connected and working together
Each processor has its own memory or access to shared memory
High-speed interconnects for communication between processors
Designed for complex, large-scale tasks in scientific research, weather simulation, cryptography, and AI
Each processor carries out part of the processing
Communication achieved via interconnected data pathways
9.1 Massively Parallel vs Cluster Computers
Massively Parallel Computers
Cluster Computers
Thousands of processors form a single tightly integrated system
Multiple independent systems networked together
Processors communicate continuously via shared architecture
Communication occurs via network, often loosely coupled
Acts like one machine with distributed processing
Group of co-operating systems (can be SIMD-based)
Higher performance, used for supercomputing
More general-purpose or batch processing systems
Example: Insurance Company Database
A popular insurance company with millions of customers uses a massively parallel processing system with 1000 nodes. When a data analyst runs a query against 100 million rows of a database, each node only bears 1/1000 of the computational load!
9.2 Link to Computer Architectures
📝 Architecture Usage
Massively parallel systems often use:
SIMD: Apply one instruction to many data points simultaneously
MIMD: Run different instructions on different data, fully independently
GPUs are massively parallel architectures with tens of thousands of threads
10. Virtual Machines
A Virtual Machine (VM) is software, not hardware. The most common type is a System Virtual Machine which is software that emulates the hardware of a real computer system. A VM is a compute resource that uses software instead of a physical computer to run programs and deploy apps.
📖 What is a Virtual Machine?
Entire operating systems running inside another operating system
Each VM runs its own OS and functions separately from other VMs
A VM can run on the same host even with different OS (e.g., MacOS VM on a Windows PC)
The principle: a process interacts directly with a software interface provided by an OS
VM management software includes a Hypervisor that monitors all activity
10.1 Key Components of Virtual Machines
📝 Guest Operating System
The OS running inside the virtual machine
Controls the virtual hardware during emulation
Being emulated within another OS (the host OS)
Runs under control of the host OS software
📝 Host Operating System
The OS that is controlling the actual physical hardware
The normal OS for the host/physical computer
Runs and monitors the virtual machine software
📝 Hypervisor (VM Monitor)
Software that creates, deletes, and manages virtual machines
Translates instructions from guest OS to host OS
Provides hardware emulation
Protects each VM so instances can be tested together
11. Benefits and Limitations of Virtual Machines
11.1 Benefits of Virtual Machines
✓ Key Benefits
Isolation: Guest OS is isolated - any issues don't affect host or other VMs
Cross-platform compatibility: Run apps not compatible with host OS by using compatible guest OS
Legacy software support: Run old software on new hardware by emulating compatible OS
Safe testing environment: Test new OS or apps without crashing the host computer
Cost efficiency: Multiple OS can exist simultaneously using same hardware only
Sandboxing: Create isolated test environments that leave host OS unaffected
Hardware emulation: Test on older hardware configurations virtually
11.2 Limitations of Virtual Machines
⚠️ Key Limitations
Performance degradation: Do not get same performance as running on original system
Resource overhead: VMs share same system hardware - over-use can exhaust CPU, disk, and memory
Cost and complexity: Building in-house VMs can be expensive for large companies
Management challenges: Complex to manage and maintain multiple VMs
Execution overhead: Extra code execution means slower app performance
Cannot judge response time: Due to performance degradation, cannot make accurate judgements
11.3 Use Cases for Virtual Machines
Use Case
Description
Cross-platform compatibility
Windows user running MacOS VM to use Mac-only software
Forward compatibility
Run older Windows version to use apps not updated for new OS
Software testing
Test apps on clean-slate systems, monitor performance impact
Development
Test against MacOS, Linux, Windows for greater compatibility
Legacy systems
Emulate old hardware/software on modern systems
💡 Exam Tip
When asked about VMs, always mention:
The Hypervisor manages and isolates VMs
VMs share physical resources but are logically isolated
Main trade-off: flexibility vs performance
12. Exam-Style Questions
1. Explain the differences between RISC and CISC processors. [6 marks]
Answer:
Instruction set: RISC has a smaller, simpler instruction set; CISC has a larger, more complex instruction set
Clock cycles: RISC instructions typically take one clock cycle; CISC instructions can take multiple cycles
Pipelining: RISC is well-suited for pipelining; CISC makes pipelining more difficult
Registers: RISC has more general-purpose registers; CISC has fewer
Control unit: RISC uses hard-wired control; CISC uses microprogrammed control
Power usage: RISC uses less power, suitable for portable devices; CISC uses more power
Applications: RISC used in smartphones/tablets; CISC used in desktops/laptops
Additional points for deeper understanding: RISC emphasises software design; CISC emphasises hardware design. RISC splits cache between data and instructions; CISC typically uses unified cache.
2. Describe the process of pipelining during the fetch-execute cycle in RISC processors. [5 marks]
Answer:
Instructions are divided into subtasks/stages (IF, ID, OF, IE, WB)
Each subtask is completed during one clock cycle
The second instruction begins in the second clock cycle, while the first has moved to its second subtask
No two instructions can execute their same stage at the same clock cycle
Multiple instructions are processed simultaneously at different stages
By the time instruction A completes, instruction F is at the first stage
Additional points: Pipeline can be flushed when a branch occurs. RISC's fixed-length instructions make pipelining more efficient.
3. Describe the four basic computer architectures (SISD, SIMD, MISD, MIMD) and give an example use for each. [8 marks]
Answer:
SISD (Single Instruction, Single Data): One processor executes one instruction on one data stream. Sequential processing. Example: Basic single-core processors, older computers
SIMD (Single Instruction, Multiple Data): One instruction applied to multiple data items simultaneously. Parallel processing. Example: GPUs, image processing, graphics cards
MISD (Multiple Instruction, Single Data): Multiple processors execute different instructions on same data. Fault tolerance. Example: Space shuttle flight control systems
MIMD (Multiple Instruction, Multiple Data): Multiple processors execute different instructions on different data. Fully parallel. Example: Multi-core CPUs, cloud computing, distributed systems
Additional points: MIMD is the most flexible architecture. MISD is rarely used in commercial applications. SIMD is particularly efficient for graphics and vector operations.
4. Explain how interrupts are handled differently in processors with and without pipelining. [5 marks]
Answer:
Without pipelining: Each instruction completes all stages before next begins. Interrupt detected at end of fetch-execute cycle. Current program stopped, registers stored, interrupt serviced, then restored
With pipelining: Multiple instructions are at different stages simultaneously. When interrupt received, several instructions may be in the pipeline
Approach 1: Discard all instructions in pipeline except the last one in WB stage, apply interrupt handler, restart from next instruction
Approach 2: Store contents of all five stages in registers, allow full restoration after interrupt serviced
Additional points: Pipelining adds complexity to interrupt handling. The goal is to ensure no data is lost and execution can resume correctly.
12. Exam-Style Questions (Continued)
5. Describe the characteristics of massively parallel computers and explain how they differ from cluster computers. [6 marks]
Answer:
Characteristics of massively parallel computers:
Thousands of processors form a single tightly integrated system
Processors communicate continuously via shared architecture
High-speed interconnects link processors
Used for supercomputing, scientific research, weather simulation
Differences from cluster computers:
Massively parallel = one machine with distributed processing; Clusters = multiple independent systems networked
Massively parallel = acts like single machine; Clusters = group of co-operating systems
Additional points: Massively parallel often uses SIMD or MIMD architectures. GPUs are examples of massively parallel architecture.
6. What is a virtual machine? Describe the roles of the host OS, guest OS, and hypervisor. [6 marks]
Answer:
Virtual Machine: Software that emulates hardware of a real computer system, allowing an OS to run inside another OS.
Roles:
Host OS: Controls the actual physical hardware. The normal OS for the physical computer. Runs and monitors the VM software
Guest OS: The OS running inside the VM. Controls virtual hardware during emulation. Runs under control of the host OS
Hypervisor: VM management software that creates, deletes, and manages VMs. Translates instructions from guest OS to host OS. Provides hardware emulation. Protects each VM
Additional points: Multiple guest OSes can run simultaneously on one host. Each VM is isolated from others.
7. Discuss the benefits and limitations of using virtual machines for software testing. [6 marks]
Answer:
Benefits:
Isolation: Testing won't crash the host computer if something goes wrong
Cross-platform testing: Test software on different OS (MacOS, Linux, Windows) using same hardware
Clean environment: Test on fresh systems without other applications interfering
Legacy testing: Test on older OS versions or hardware configurations
Cost effective: Only need one physical machine instead of multiple
Limitations:
Performance degradation: Cannot accurately judge response time due to overhead
Resource limitations: VMs share hardware - heavy testing can exhaust resources
Complexity: Managing multiple VMs can be complex
8. Tick one box in each row to show if the statement applies to RISC or CISC processors. [4 marks]
Answer:
Statement
RISC
CISC
Uses a smaller instruction set
✓
Uses single-cycle instructions
✓
Uses fewer general-purpose registers
✓
Uses both hardwired and micro-coded control unit
✓
12. Exam-Style Questions (Continued)
9. Explain how RISC processors make use of pipelining to improve performance. Include the role of registers. [6 marks]
Answer:
RISC processors use fixed-length instructions that each take one clock cycle, making pipelining easier
The fetch-decode-execute cycle is split into five stages: IF, ID, OF, IE, WB
While one instruction is being executed, the next is being decoded, and another is being fetched
This allows multiple instructions to be processed simultaneously at different stages
Registers play a key role: RISC has many general-purpose registers that store intermediate values between stages
Using registers instead of RAM reduces memory bottlenecks, allowing pipelining to run smoothly
All operations can be done efficiently within the CPU using registers
Additional points: Hard-wired control unit in RISC allows faster stage execution. Fixed-length instructions make decoding predictable and efficient for pipelining.
10. A developer needs to test a new application on three different operating systems (Windows, Linux, and MacOS). Explain how virtual machines could be used for this purpose and discuss the benefits and drawbacks of this approach. [8 marks]
Answer:
How VMs would be used:
Install a hypervisor on the developer's physical machine (host OS)
Create three virtual machines - one running Windows as guest OS, one running Linux, one running MacOS
Install the application on each VM and test its functionality
The hypervisor translates instructions and provides hardware emulation
Benefits:
Multiple OS simultaneously: Can test all three using same hardware
Reduced cost: No need for three separate physical machines
Isolation: Problems in one VM don't affect others or the host
Convenience: Easy to switch between test environments
Drawbacks:
Performance overhead: Extra code execution means slower app performance
Cannot judge response time: Performance differs from native execution
Resource usage: Three VMs require significant CPU, RAM, and storage
13. Glossary
📖 Key Terms
CISC (Complex Instruction Set Computer): Processor architecture with a large set of complex instructions that can perform multi-step operations in a single instruction
RISC (Reduced Instruction Set Computer): Processor architecture with a smaller set of simple instructions, each typically executed in one clock cycle
Pipelining: Technique where multiple instructions are processed simultaneously at different stages of the fetch-decode-execute cycle
Instruction Set Architecture (ISA): The set of basic instructions that a processor understands
Opcode: The operational code part of an instruction specifying the operation to perform
Operand: The data or memory location that an instruction operates on
SISD: Single Instruction, Single Data - one processor executes one instruction on one data stream
SIMD: Single Instruction, Multiple Data - one instruction applied to multiple data items simultaneously
MISD: Multiple Instruction, Single Data - multiple processors execute different instructions on the same data
MIMD: Multiple Instruction, Multiple Data - multiple processors execute different instructions on different data
📖 Key Terms (Continued)
Massively Parallel Computer: System with thousands of processors working together to solve large problems
Virtual Machine (VM): Software that emulates a physical computer system
Guest OS: The operating system running inside a virtual machine
Host OS: The operating system controlling the physical hardware on which VMs run
Hypervisor: Software that creates, manages, and monitors virtual machines
Interrupt: Signal that temporarily stops the current process to handle an event
MIPS: Millions of Instructions Per Second - a measure of processor speed
Clock Cycle: The basic unit of time in a processor, during which one operation can occur
Register: Fast, temporary storage inside the CPU for data being processed
Control Unit: Component that directs operation of the processor
Microcode: Low-level instructions that implement machine code instructions in CISC processors